The present subject matter relates to a semiconductor design technology, and in particular, to a clock alignment training operation, which is required in a high-speed semiconductor memory device. More particularly, the present subject matter relates to a circuit which can convert an unstable phase comparison result into a stable state and transmit the converted stable state to an external controller even though the unstable phase comparison result is caused by a noise or a jitter in a process of comparing a data clock with a system clock under clock alignment training operation.
In a system including a plurality of semiconductor memory devices, the semiconductor memory devices are used to store data. When a data processor, for example, a memory control unit (MCU) requests data, the semiconductor memory device outputs data corresponding to an address input from a device requesting data, or stores data provided from the data requesting device in a position corresponding to the address.
To this end, a high-speed memory device, which has been recently developed, is designed in order to input/output two data between the rising edge and falling edge of an external system clock and to input/output two data between the falling edge and a next rising edge of the external system clock. That is, the high-speed memory device is designed in order to input/output four data in one cycle of a system clock.
However, since the system clock is merely represented as two states, i.e., logic high or logic low, a data clock having two times faster frequency than that of the system clock is required for inputting/outputting four data during one cycle. That is, an exclusive clock for the input/output of data is required.
Accordingly, when an address and a command are received/transmitted, the high-speed semiconductor memory device uses the system clock as a reference clock. When data are inputted/outputted, the high-speed semiconductor memory device performs controls in order for the data clock to have a frequency two times higher than that of the system clock using the data clock as the reference clock.
That is, the high-speed semiconductor memory device repeats two cycles of the data clock in one cycle of the system clock, and inputs/outputs data at rising and falling edges of the data clock respectively. Therefore, the high-speed semiconductor memory device can input/output four data during one cycle of the system clock.
In this way, the high-speed semiconductor memory device exchanges data using two clocks having different frequencies for performing a read or write operation, as opposed to a conventional Double Data Rate (DDR) synchronous memory device which uses one system clock as a reference clock for performing a read or write operation.
However, in a case where a phase of the system clock and a phase of the data clock are not aligned, a reference for transferring an operation command and an address is not aligned with a reference for transferring data. This denotes that the high-speed semiconductor memory device cannot normally operate.
Therefore, to normally operate the high-speed semiconductor memory device, an interface training operation between the high-speed semiconductor memory device and a data process device must be performed at an initial operation.
Herein, the interface training is to train an interface for transferring commands, addresses, and data between the semiconductor memory device and the data process device to operate at an optimal time before a normal operation.
The interface training is categorized to clock alignment training (WCK2CK training), read training, and write training. In the clock alignment training (WCK2CK training), the data clock and the system clock are aligned.
FIG. 1 is a block diagram of a circuit for performing the clock alignment training in accordance with a conventional technology.
First, in the basic principle of the clock alignment training, the high-speed semiconductor memory device receives an address signal and a command signal from an external controller on the basis of the system clock HCK, and outputs data stored in the semiconductor memory device to the external controller on the basis of the data clock WCK as described above.
Accordingly, when there is a phase difference between the system clock HCK and the data clock WCK, the data stored in the semiconductor memory device reach the external controller more quickly or more slowly by a time corresponding to the phase difference.
Consequently, the clock alignment training is an operation of the high-speed semiconductor memory device that detects a phase difference between the data clock WCK and the system clock HCK applied from the external controller at an initial operation, transmits the detection result to the external controller, and thus reduces the phase difference between the system clock HCK and the data clock WCK.
That is, in the circuit for performing the clock alignment training in accordance with the conventional technology illustrated in FIG. 1, the circuit receives the data clock WCK and the system clock HCK from the external controller, detects the phase difference between the data clock WCK and the system clock HCK, and transmits the detection result to the external controller.
Referring to FIG. 1, the circuit includes a clock inputting unit 100 receiving the system clock HCK for synchronizing an input time of the address signal and an input time of the command signal and the data clock WCK, which has a frequency higher than that of the system clock HCK, for synchronizing an input time of the data signal from the external controller, a frequency converting unit 120 converting a frequency of the data clock WCK in order for the data clock WCK to have the same frequency as that of the system clock HCK, a phase detecting unit 140 detecting a phase of a clock DIV_WCK output from the frequency converting unit 120 on the basis of a phase of the system clock HCK and generating a detection signal DET_SIG corresponding to the detection result, and a signal transmitting unit 160 transmitting the detection signal DET_SIG as a training information signal TRAINING_INFO_SIG to the external controller. The circuit includes a clock inputting unit 100 includes a data clock input pad 106, a data clock input buffer 108, a system clock input pad 102, and a system input buffer 104. The signal transmitting unit 160 includes a training information output buffer 162 and a training information output pad 164.
FIG. 2 is a timing diagram illustrating an operation waveform of a case where the circuit for performing the clock alignment training in accordance with the conventional technology of FIG. 1 normally performs the clock alignment training.
Referring to FIG. 2, although a frequency of the data clock WCK, which is input to the circuit for performing the clock alignment training in accordance with the conventional technology from the external controller, is higher than that of the system clock HCK, it can be seen that a frequency of the data division clock DIV_WCK output from the clock dividing unit 120 is the same as that of the system clock HCK, because the clock dividing unit 120 changes a frequency of the data clock WCK in order for the frequency of the data clock WCK to be the same as that of the system clock HCK.
Moreover, clock edges are not synchronized with one another at a section {circle around (1)} before the performing the clock alignment training operation. That is, it can be seen that the phase of the data clock WCK and the phase of the data division clock DIV_WCK are not synchronized with the phase of the system clock HCK at the section {circle around (1)} before the performing the clock alignment training operation.
The circuit changes the phase of the data clock WCK and the phase of the data division clock DIV_WCK in a state where the phase of the system clock HCK is constant, in order to synchronize the phase of the data clock WCK and the phase of the data division clock DIV_WCK with the phase of the system clock HCK at sections {circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (5)}, and {circle around (6)} after the starting of the clock alignment training operation.
At this point, a phase of the data clock WCK and a phase of the data division clock DIV_WCK are changed in correspondence with a logic level of the training information signal TRAINING_INFO_SIG which is transmitted to the external controller by the signal transmitting unit 160.
Moreover, at the sections {circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (5)} and {circle around (6)} when the phase of the data clock WCK and the phase of the data division clock DIV_WCK are not synchronized with that of the system clock HCK so that they need to be changed, the logic level of the training information signal TRAINING_INFO_SIG continuously maintains a logic low state. However, in a section {circle around (7)}, in which the phase of the data clock WCK and the phase of the data division clock DIV_WCK are synchronized with that of the system clock HCK so that it is unnecessary to change the phase of the data clock WCK and the phase of the data division clock DIV_WCK, the logic level of the training information signal TRAINING_INFO_SIG continuously maintains a logic high state.
As a result, in the circuit for performing the clock alignment training, the phase detecting unit 140 continuously compares the phase of the data clock WCK with the phase of the system clock WCK until the phase of the data clock WCK input from the external controller by the clock alignment training operation is synchronized with that of the system clock HCK, and thereafter the training information signal TRAINING_INFO_SIG is transferred to the external controller according to a result of the comparison.
FIG. 3 is a timing diagram illustrating an operation waveform of a case where the circuit for performing the clock alignment training in accordance with the conventional technology of FIG. 1 abnormally performs the clock alignment training by a jitter.
Referring to FIG. 3, the operation waveforms of the sections {circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (5)}, and {circle around (6)} from a time when the clock alignment training is started at section {circle around (1)} before performing the clock alignment training operation to a time when the phase of the data clock WCK is synchronized with the phase of the system clock HCK are the same as the operation waveforms of the case of FIG. 2. In the case of FIG. 2, the clock alignment training operation is normally performed. The operation waveforms are changed from a state where the phase of the data clock WCK, which is inputted to the circuit for performing the clock alignment training according to a conventional technology from the external controller, is not synchronized with that of the system clock HCK to a state where the phase of the data clock WCK is synchronized with the phase of the system clock HCK.
That is, the phase of the data clock WCK and the phase of the data division clock DIV_WCK are changed according to the logic level of the training information signal TRAINING_INFO_SIG which is transmitted to the external controller by the signal transmitting unit 160 in a state where the phase of the system clock HCK is constant, and thus the phase of the data clock WCK is synchronized with that of the system clock HCK.
However, unlike the operation waveforms of FIG. 2, at a time {circle around (6)} when the clock alignment training is normally performed so that the phase of the data clock WCK is synchronized with that of the system clock HCK, a phenomenon that the phase of the data clock WCK and the phase of system clock HCK are changed by a noise or a jitter can occur, and, consequently, the phase of the phase-synchronized data clock WCK is not synchronized with the phase of the phase-synchronized system clock HCK as shown in the sections {circle around (7)} and {circle around (9)}.
Specifically, the logic level of the training information signal TRAINING_INFO_SIG continuously maintains a logic low state at the sections {circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (5)}, and {circle around (6)} where the phase of the data clock WCK and the phase of the data division clock DIV_WCK are not synchronized with that of the system clock HCK so that they need to be changed. The logic level of the training information signal TRAINING_INFO_SIG is changed into a logic high level at a time {circle around (6)} when the clock alignment training is normally performed so that the phase of the data clock WCK is synchronized with that of the system clock HCK. However, the phase of the system clock HCK is immediately changed by a noise or a jitter as shown in section {circle around (7)} of FIG. 3 so that the phase of the data clock WCK is not synchronized with that of the system clock HCK, and, consequently, the logic level of the training information signal TRAINING_INFO_SIG is again changed into a logic low level.
Likewise, as soon as the logic level of the training information signal TRAINING_INFO_SIG is again changed into a logic low level due to the phase change of the system clock HCK by a noise or a jitter, the phase of the data clock WCK is again changed, and thus the phase of the data clock WCK is again synchronized with the phase of the system clock HCK as shown at a section {circle around (8)} of FIG. 3. However, the phase of the data clock WCK is immediately changed by a noise or a jitter as shown at a section {circle around (9)} of FIG. 3 so that the phase of the data clock WCK is not synchronized with the phase of the system clock HCK, and, consequently, the logic level of the training information signal TRAINING_INFO_SIG is again changed into a logic low level.
As described above, although the circuit for performing the clock alignment training in accordance with the conventional technology synchronizes the phase of the data clock WCK with the phase of the system clock HCK by performing the clock alignment training, the phase of the data clock WCK and the phase of the system clock HCK may be changed by a noise or a jitter, unlike a phase in synchronizing them with each other, and consequently the logic level of the training information signal TRAINING_INFO_SIG, which is transmitted to the external controller to inform a result of the clock alignment training operation, may continuously be charged from a logic low level to a logic high level or from a logic high level to a logic low level.
In this way, when the logic level of the training information signal TRAINING_INFO_SIG is continuously charged by a noise or a jitter, a confusion occurs in the external controller that must synchronize the phase of the data clock WCK with the phase of the system clock HCK on the basis of the logic level of the training information signal TRAINING_INFO_SIG and transmit the data clock WCK and the system clock HCK to the semiconductor memory device, and thus a very long time may be required for performing the clock alignment training or a malfunction can be caused by a wrong clock alignment training.